The largest pattern a lithography scanner can print in one exposure is 26 × 33 mm, and that number has barely moved in thirty years. The systems we build out of silicon have grown by orders of magnitude anyway. Each time one level of the hierarchy runs out of room, scaling moves up a level.
Scroll to zoom out from one die to a data hall: how it’s built today on the left, and how it could be built in 2030 on the right.
01 / 06
~200 M → ~300 M per mm²
The field that never grew
Today
A reticle-sized die on N3P, the 3 nm-class process behind Rubin: about 858 mm², as large as one exposure can print. That 26 × 33 mm field has been fixed since the DUV stepper era.
2030
Still the same field. On TSMC’s A12, with Super Power Rail backside power delivery, the die packs roughly 1.5× today’s transistors into the same 26 × 33 mm. The 12-inch masks planned for High-NA EUV keep that field rather than enlarging it.
02 / 06
~200 M → ~550 M per mm²
Going vertical
Today
No stack. The die is a single layer, and its memory sits millimeters away in HBM stacks on the interposer.
2030
Hybrid bonding joins dies copper to copper, at about 4.5 µm pitch by 2030 (6 µm today). Under the logic die go a memory die and a photonic I/O die, so memory is microns away and data leaves as light. Heat sets the limit: one hot logic layer per stack.
03 / 06
~100 M → ~420 M per mm²
Side by side, then panel-wide
Today
CoWoS-L on a round 300 mm wafer. Rubin puts two compute dies, two I/O dies and eight HBM4 stacks on a ~4× reticle interposer, with silicon bridges where dies talk. TSMC is producing up to 5.5× today.
2030
CoPoS builds the interposer on a square 310 × 310 mm panel instead of a round wafer, so packages grow to about 16× reticle, four per panel. A dozen stacks wire together through its redistribution layers and behave like one large chip. Larger 515 × 510 mm panels are likely to come after 2030.
04 / 06
~4.5 M → ~30 M per mm²
The board changes jobs
Today
A Vera Rubin compute tray carries four GPU packages and two Vera CPUs, plus ConnectX-9 NICs and a BlueField-4 DPU. NVLink still runs over board traces to copper connectors at the back.
2030
Copper reach halves every time lane rates double: 3 m at 56G, 1 m at 224G. So fast signals skip the board, by fiber from the photonic dies and by flyover cable. Each board carries two CoPoS packages and two CPUs, about 30 kW. Two is the practical limit: four would need ~60 kW and ~80,000 A in one tray, more than its power stages and cold plates can handle.
05 / 06
~50 M → ~340 M per mm²
The rack is the computer
Today
An NVL72 rack: 18 compute trays and 9 NVLink switch trays joined by a copper cable spine, for 72 GPUs in one scale-up domain. Four power shelves feed it.
2030
The same layout as today, 18 compute boards and 9 switch trays, now draws about 600 kW. That fits within the 1 MW racks Nvidia is planning on 800 V DC power. Power and cooling, not space, set the ceiling: a full 1 MW rack could take about 30 boards. Optics leave every stack, cutting energy per bit from more than 30 pJ toward under 5 pJ, and below 2 pJ with optics in the stack.
06 / 06
~11 M → ~36 M per mm²
Where physics takes over
Today
Racks connect through switches over pluggable optics, so tight coupling ends at the rack. The 28 racks drawn here draw about 6 MW, and each takes about 3 m² of floor once aisles are included.
2030
Light in fiber covers about 5 ns per meter. The dashed ring has a radius of about 4 m, roughly 20 ns of fiber, which is about the reach of tightly coupled work. The same 28 racks now draw about 17 MW, and at 600 kW each they need room for switchgear and coolant distribution, about 6 m² of floor per rack. At this scale the binding limit is power.
The full map
Read it top to bottom, in the same order as the animation. Each level exists because the one above it ran out of room.
| Level | Scaling lever | Binding limit |
|---|---|---|
| Die | Chiplets, CFET | Fixed 26 × 33 mm reticle field |
| 3D stack | SoIC hybrid bonding (memory, photonic I/O) | Heat and power delivery |
| Panel | CoPoS, glass core substrates | Flatness and overlay past ~500 mm |
| Board | Flyover cables and fiber | Copper reach halves per rate doubling |
| Rack | Copper cable spine | Power per rack, cable reach |
| Data hall / campus | Co-packaged optics | Speed of light (~5 ns per meter) |
| Every level | Power delivery, cooling, known-good-die yield |
The limits near the top of the table are manufacturing problems, and money and time solve them. The ones further down are physics, which you can only route around. Power and heat decide how far every lever goes.
Roadmap figures (CoPoS panel formats and timing, SoIC pitches) reflect public TSMC and industry reporting as of late 2026, and they tend to move between symposium cycles.
Transistor density in the animation is the logic transistor count at each level divided by the footprint it occupies. Memory bits in HBM are not counted. Today’s figures use Nvidia’s published counts: 336 billion per Rubin GPU, split across two compute dies, and 227 billion per Vera CPU. They assume a ~4× reticle interposer, a ~0.4 m² compute tray (the same board area is used for 2030), a ~0.64 m² rack footprint, and ~3 m² of hall floor per rack including aisles. The 2030 figures are estimates for a system in volume production by 2030. They assume TSMC A12 logic with backside power at about 1.5× N3P density (TSMC has not published absolute densities; this compounds its stated N2, A14 and backside-power gains), a memory layer adding ~250 M/mm², twelve stacks in a ~120 × 112 mm (~16× reticle) package built on a 310 × 310 mm CoPoS panel, two packages and two A12-class CPUs (~340 B transistors each) per ~0.4 m² board, and the same rack layout as today: 18 compute boards and 9 switch trays (~600 kW). At that power each rack is assumed to need ~6 m² of hall floor, double today’s, to leave room for switchgear, 800 V DC conversion and coolant distribution.
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